How To Shift Register Content In Systemverilog

Verilog Shift Register

Posted by in Verilog / VHDL on ii-12-13

Shift registers are a fundamental office of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the compages pipeline.

This article will cover the following concepts:

Shift Register Concepts
Verilog Implementation
Synthesis Considerations
Typical Uses

For a VHDL shift register, see our respective shift annals article with example code and VHDL specific tips.

Shift Annals Concepts

A shift register is a series of continued registers (flip-flops) that are sequentially connected together and then that a value at the input is passed from 1 register to the next on each clock cycle. In some designs, every register element tin be accessed individually, while other implementations but allow access at specific locations. An illustration of a shift register is shown below, where information is entering the register chain at the to the lowest degree pregnant fleck (LSB), or the right side of the picture.

Shift Register

The in a higher place illustration shows a single-bit wide shift register with a length of eight, but there is nix special about those numbers. Depending on the implementation method (code or IP), any practical dimensions can be used.

A single-bit shift register can be implemented in Verilog using concatenation. If you want to shift multiple bits at a time (e.yard. a byte, word, double give-and-take, etc.), the shift annals must use a for loop. This is because Verilog does not allow bulk addressing of memory types, which is how Verilog classifies two dimensional arrays.

The code example implements both a single- and multi-fleck shift register.

Verilog Shift Annals Lawmaking

[cc lang="verilog" noborder="true" tab_size="4″ lines="-1″ width="600″ escaped="truthful"]
module shift_register_v(
input CLK,
input RST,
input DATA_IN,
output BIT_OUT,
output [7:0] BYTE_OUT
);

//————————————————————–
// bespeak definitions
//————————————————————–

//shift register signals
reg [7:0] bitShiftReg;
reg [7:0] byteShiftReg[11:0];
integer i;

//————————————————————–
// shift register
//————————————————————–

//shift annals
always @(posedge CLK)
brainstorm

//bit shift register
bitShiftReg <= {bitShiftReg[6:0],DATA_IN};

//byte shift register
byteShiftReg[0] <= bitShiftReg;
for(i=i;i<12;i=i+1)
byteShiftReg[i] <= byteShiftReg[i-1];
cease

//————————————————————–
// outputs
//————————————————————–

//module output wires
assign BIT_OUT = bitShiftReg[7];
assign BYTE_OUT = byteShiftReg[11];
[/cc]

Synthesis Considerations

Seemingly small differences in Verilog code will produce different results when implemented inside a real FPGA. One of the nearly important is how you reset the shift annals–applying a reset to all the registers (every bit shown in the example) or only the first register.

Using a reset on the entire register depository financial institution volition potentially cause an increase in resource utilization in the FPGA. Since some architectures only back up a single reset line for a grouping of flip-flops, forcing each register to reset may cause only one flip-flop in a group to be utilized, stretching the blueprint across several configurable logic blocks (CLBs). In many FPGAs, a more than compact design is synthesized when the reset only needs to be applied to one register element.

Other coding considerations involve ensuring that the size of your shift register is appropriate for the targeted block RAM (BRAM) in the FPGA. Matching the width of a BRAM, for instance, can go a long way to allowing the blueprint to run at the highest speed.

As well manually coding the shift annals in Verilog, you lot may choose to use built-in cores from the manufacturer that optimize the blueprint according to the architecture of the specific FPGA (Xilinx calls these IPCores). I typically code the shift register in Verilog if the length volition be short and I will need information from multiple delays. If only one tap is needed, or the shift register needs to be adequately long, I volition use the IPCore.

Typical Uses

Shift registers are used whenever you'd like to delay the information betoken by one or more than clock cycles so that you can employ it later–either for a information operation or output. One common instance would be to equalize the filibuster of two parallel signals–possibly a data and a information valid indicator. Often a data valid indicator is delayed to match the latency of operations performed on the data stream.

More Resource

If you're new to Verilog coding, it'southward often helpful to simply read through a practiced text book on the subject. My favorite volume on Verilog is Verilog HDL past Samir Palnitkar. This book covers corking detail of how to approach designs in Verilog, from bones syntax to implementation examples. The volume does accept a slant towards simulation at the beginning, but the affiliate on synthesis constraints round out the material nicely. This is my become-to book for Verilog.

Happy coding!

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